Mapping an Argument Essay

The real issue here is rather or not marijuana should be legalized. There are both pro’s and cons with legalization of marijuana, many would argue that alcohol is more dangerous and damaging to the body that marijuana is while others would argue that marijuana is an addictive drug, and a gateway to other more serious drugs. The pros of medical marijuana seem to outweigh the cons being how more and more states are starting to legalize the use of it. Also, it was found that it does help with serious medical issues. The premise would be the fight for legalizing marijuana, and the unstated premises would be medical marijuana. The federal government says that marijuana has a high potential for abuse and has no medical value but â€Å"As of 2012 sixteen states, including Alaska, Arizona, California, Colorado, Delaware, Hawaii, Maine, Michigan, Montana, Nevada, New Jersey, New Mexico, Oregon, Rhode Island, Vermont, and Washington, and the District of Columbia have legalized medical marijuana†. The bottom line is that a large group of Americans support the legalization of marijuana for medical purposes and many Americans support marijuana for recreational purposes as well. In fact, the state of Colorado was the first state to legalize marijuana for recreational purposes therefore in my opinion that has to soften a lot of people’s opinion regarding the use of medical marijuana. According to the Great Falls, Montana,  Tribune, at an October 2009 medical marijuana health screening in that city, a Dr. Patricia Cole of Whitefish examined 150 patients in 14 and half hours who were there to see if they qualified to receive medical marijuana. Many find it hard to believe how easy it is to receive medical marijuana, â€Å"Some submitted paperwork and payment for the â€Å"examination† and an additional $25 registration fee is all it takes to be issued a card, as no formal medical records are required, only a stated complaint such as chronic headaches or insomnia or back pain†. Urban and small towns are affected the most by these medical marijuana controversies â€Å"Missoula, population 70,000, is home to the University of Montana. There are a dozen storefront outlets and 400 registered caregiver/growers serving 1,800 (and growing) card carriers. † The premise would be medical marijuana and the unstated premise would be the legalization of medical marijuana. Since the legalization of medical marijuana many small towns across America have been affected in a negative way. A lot of people started to see dollar signs and a lot of medical marijuana dispensaries were open. The opening of these medical marijuana dispensaries in these small towns and all across America caused a huge uproar and made many people go against it. The bottom line is that a lot of these small towns learned their lesson and made tougher standards regarding medical marijuana and started to do a better job in regulating the use of it. http://ic. galegroup. com. ezproxy. apollolibrary. com/ic/ovic/ReferenceDetailsPage/ReferenceDetailsWindow? failOverType=&query=&windowstate=normal&contentModules=&mode=view&displayGroupName=Reference&limiter=&currPage=&disableHighlighting=true&displayGroups=&sortBy=&source=&search_within_results=&action=e&catId=GALE%7C00000000LVXO&activityType=&scanId=&documentId=GALE%7CPC3010999128 ttp://ic. galegroup. com. ezproxy. apollolibrary. com/ic/ovic/ViewpointsDetailsPage/ViewpointsDetailsWindow? failOverType=&query=&prodId=OVIC&windowstate=normal&contentModules=&mode=view&displayGroupName=Viewpoints&limiter=&currPage=&disableHighlighting=true&displayGroups=&sortBy=&source=&search_within_results=&action=e&catId=&activityType=&scanId=&documentId=GALE%7CEJ3010753218

Conserve and Preserve Essay

With today’s growing population, resource consumption is becoming a huge concern. It is important that humans realize what is best for both our present and future generation, and what is best for our planet. We must preserve certain areas from being destroyed to keep their natural beauty. We should also conserve resources, so they can continue to flourish, but also so we can continue to live our lives without depleting these resources. Every individual unit of the environment works together to maintain a balance that supports the cycle of life. Humans must co-exist in a positive way with these units. We should live in a way that does not exploit any part of nature. We should not only respect and sustain the environment for our own benefit and for future generations, but also because nature itself is good on its own. When looking at preservation and conservation, there is not one that is better the other. Like many other rules and sets of standards, there are exceptions. Preservation is the action of protecting a certain thing or area completely. Conservation is a form of preservation, where we can use a particular resource or portion of land, in this case, but it is used sparingly and sustainably. There are certain situations where preserving something is beneficial. Then there are other situations where conserving something would be better for a larger number of living things. It would be ideal to say that we should strive to preserve nature in all scenarios but that is not a practical approach because there are certain needs that we as human beings have to fulfill that we can only get from nature. Certain medicines that keep people alive can be found in nature. If for instance a plant has the ability to save someone’s life, then it would be acceptable to cut that plant down to help heal the patient. There are some exceptions to this of course. It would be wrong to cut down the plant if it was unable to be replaced. The plant should be plentiful and able to thrive as a species before we use it to help our own species. For the most part, humans are put on a higher scale than some other species. This is not to say that we should disregard those species or over-use them, but if it came down to a life or death situation for a person, using the plant would be ethical. There are other scenarios in which preservation would be a better approach. An example of this is mountaintop removal. It does not seem ethical to be destroying such a beautiful object that forms naturally just so that we can have access to coal seams. The coal extracted from the mountain is only beneficial for a certain amount of time but the negative consequences from the whole process will be felt a lot longer (Copeland). Even though the mountain itself since it is not a living, breathing organism, it is important to respect the natural beauty of the mountain. The animals and plants that may reside on the mountain are also affected by this, and that should be taken into consideration. Another example of a time when it is best to preserve is in the case of an endangered organism. Say for instance that a certain tree is being cut down at an alarming rate to make paper. The tree will cease to exist if we continue at the rate that we are going. Then we should stop all chopping down of that particular tree. We should preserve it and allow it to continue to live, not just so that in the future we still have that tree around to produce more paper, but because it is a living thing that has value on its own. Our population is growing, and we have to figure out the best way to use our resources. Garrett Hardin also recognizes this as a problem in his essay â€Å"Lifeboat Ethics†, but takes the stance that if we help the poor people; we are hurting them in the long run. He believes that the biggest factor for overpopulation is the fact that poor countries multiply and increase their population at a much faster rate than countries that are predominately rich. Because of this, the problems associated with too many people in one area will continue to grow larger. This is because rich countries have the resources to support their people more so than the poorer countries that cannot even begin to help their people (Hardin). Getting food is a major concern of many people who think that overpopulation is becoming a problem. Hardin also recognizes this as a problem, but takes the stance that if we help the poor people; we are hurting them in the long run. Conservation becomes important when taking the population into consideration. Overpopulation will have a large impact on the environment because there will obviously be more of a need for basic elements such as water, food, and shelter. With more people demanding food, more livestock will need to be bred; more fruits and vegetables will need to be grown. With more people demanding shelter, more land will need to be plowed in order to build houses. With more people on the earth demanding water, more freshwater sources will be dried up. Not only are the necessities factored into the problem but with more people, all the luxuries and small things will add up also. There will be a higher demand of medicines, paper, and other goods that we can get from nature. The increase of human life will create a huge blow for the environment. It is important that we prevent our world from becoming a commons open to everyone, where people use their resources foolishly and greedily. Since people are part of the whole equation that makes up the environment, we should care and respect others. However, in feeding the poor, they do not realize their problems and continue to reproduce, thus putting them and the country in a deeper hole. This too has an effect on the environment because in the search for food, people do things that do not support a sustainable cycle. An example of this is the fact that since there are more people and getting meat to them is a long process, factory farms have taken the place of actual farms. Animals are now bred to grow faster and jacked up with hormones in an attempt to get them to the slaughterhouse faster so that the demands of consumers can be met. Also in order to keep up with more people, that means that there must be more animals to begin with. Livestock are crowded into small cages where they are unable to turn around, they are not able to live with their young, they pick up diseases and many other problems arise from this. This affects the life of the livestock obviously, but also affects the life of the consumer who then eats the meat. It is understandable that individuals want to eat meat because they say it tastes good, it is high in protein, and it’s convenient as well. However, the way that humans do it is immoral and wrong. We do not give the animals any chance of survival or even a chance at life to begin with. It would be more justifiable for people to go out and hunt their meat like people used to do. Then the animals would be able to live a normal life up until they were killed. This would also cut down on the air pollution that comes from factory farms, reduce the amount of water that is needed to produce meat, reduce the amount of crop space that is needed to feed the livestock, and reduce the amount of drugs that the consumer also eats after the animals are fed them. This brings the argument back around to the fact that the population is growing and that there are starving people all around the world. If reduced their consumption meat, then there would not be as big of a need for livestock. Thus the crops that are grown to feed the cows could be fed to the people who need it. We could also stop cutting down trees and destroying forests that is normally needed in order to make room for all that food that needs to be produced. Around the world 756 million tons of grain is fed to livestock and almost half of the 225 million tons of soy that is produced yearly also goes to feed the animals that we eat (USDA). These crops could be used to feed people in starving countries. It could affect the lives of people right here in America. Our population is growing very quickly and resources are becoming scarcer every day. We should want to preserve and conserve the natural world around us. Whether a person believes that another living thing has rights or not, they should still treat it with respect and care. One person or a small group of people should not make the ultimate decisions on what is considered worthy of life or unworthy. If people took the time to consider the feelings and consideration of the living things in nature, the world would be a better place not just for us now, but for future generations.

Appearance May Not Be Reality Research Paper Example | Topics and Well Written Essays - 500 words

Appearance May Not Be Reality - Research Paper Example It is illegal to report data falsely. General hospital would be liable if patients such as, the Jones family, sustained infection after seeking treatment from the hospital (Pozgar, 2013). Several elements of the ACHE code of ethics would help an administrator of General hospital in determining the right course of action to take. One of those elements is the one that encourages healthcare management to disclose conflicts of interest. Another element appropriate to this case is one that admonishes healthcare executives to desist from taking part in activities that are demeaning to the credibility and dignity of the profession of the management of healthcare. The administrator can invoke the element of the ACHE code of ethics that calls for them to ensure patients are informed about opportunities, responsibilities and risks involved in certain healthcare services. A General hospital administrator should also implore the guidance of the ACHE code of ethics that would help resolve any conflict that would emerge between patients and the organization’s personnel. Additionally, it would be appropriate to refer to the ACHE code of ethics that promotes the need to have evidence-based clinical practices in a healthcare organization. The administrator’s course of action should be guided by the element that promotes the use of sound business practices. It is advisable for the administrator to follow the element on truthful dissemination of information (ACHE, 2014). Members of General Hospital’s ethics committee should push an assessment of hospital staff awareness and attitudes towards bioethics. These members should convene departmental meetings to discuss the issue of faulty reporting. Ethics committee members should liaise with nursing managers in working a way out of the problem created by the issue. They need to reach out to ethics committees of other healthcare organizations and learn

Transparency in the cost of justice Statistics Project - 1

Transparency in the cost of justice - Statistics Project Example One of the major impediments with EU legal system is the hefty fee for lawyers and the reason for this is four-fold. Secondly, significant differences in sources and levels of costs from one member state to the other also constitute a barrier. Thirdly, the high costs in relation to the quantity of litigations frequently act as an obstacle. Fourthly, significant differences among the member states legal systems entail enhanced costs to initiate cases as the litigant has to pay for translators and lawyers apart from bearing the expenditure on travel and notifications. This study contains an analysis of data on four types of costs for four case studies based on the data acquired from 28 European countries. Cost data has been taken under four heads, such as court costs, lawyer costs, bailiff costs and appeal costs. Court cases of four types have been considered and the costs are calculated for all cases. The categories of cases include CA1A: National situation, in which a couple gets mar ried and subsequently they separate and agree for a divorce, CA1B: Transnational situation. That is two nationals from a similar member state get married and afterward file for a divorce, CA4A: National situation, which includes commercial and contract law and CA4B: Comprising transnational situation in Commercial Law and Contract. The above graph represents CA1A: National situation where a couple gets married. Later they separate and agree to a divorce in different European countries. It can be seen that the lawyer cost in the instant case is common in all countries. Italy has a high lawyer cost in CA1A. Ireland, Poland, Luxembourg, Estonia, Austria, UK are comparatively cheaper in lawyer fee. Lawyers, as legal experts deal with legal costs that have a bearing on the restoration of the privileges of litigants to carry out the litigation costs. The costs are better in UK probably because of transparent court procedures. Lawyers’ fees form the most significant part of the

Explore the way in which one or more emotional state is elicited and Essay

Explore the way in which one or more emotional state is elicited and shaped by a particular film, focussing on the consequences of formal and stylistic choices for our emotional experience of the film - Essay Example These include hypnosis, repeated phrases, music and facial muscle movement. Of all the methods used in elicitation of emotions, films are the only easily standardized method and entail little deception that is mostly seen in other methods. Films also present a higher degree of ecological acceptability in that they combine both the visual and auditory stimuli. As a consequence of the combination, films easily elicit a variety of emotions. The ability of a film to evoke an emotion is then compared to other films (Plantinga, 2009, p.71). Films can also elicit various cognition patterns to the audience. General cognition such as memory, assimilation and meta-cognition are enhanced by the film. Most cognitive effects of films relates to the information presentation and the atmosphere induced by the film. It is a normal phenomenon for instance, violence film to elicit violence. The elaboration of this effect is related to the significant cognitive effects of the film. The film Crash elicits a variety of emotional state in the audience. The emotional states elicited majorly relates with the theme of the film and the characters’ interaction in the film (Coan & Allen, 2007, p. 52). Crash is a recent film produced in 2004. Paul Haggis is the producer, co-writer and also contributed to its direction. The film addresses two major concerns including racial tension and the social tension in Los Angeles, California. Crash was inspired by a real life experience where Haggis Porsche was suffered a carjacking in 1991 at Wilshire Boulevard (Villalba & Redmond 2008, p. 72) The characters for the story include a white attorney and the wife, a black detective who had a younger brother and a gang associates. There is a white racist police officer who annoys his more critical partner. It entails a Persian immigrant and an industrious Hispanic locksmith who is a family man. The films stand outs distinctively from other films in that is relatively

Emloyee Engagement Assignment Example | Topics and Well Written Essays - 3000 words

Emloyee Engagement - Assignment Example Organisations are constantly searching for the new and improved ways that can enable them to stay ahead of their competitors by creating efficient and effective competitive advantages. For this reason, employers have realised that this goal can only be achieved by shifting their focus to employee engagement, even though, opponents of employee engagement argue that it is not be the real cure for all the problems that the organisations face today. However, the implementation of the engagement strategies is a key to the overall organisational effectiveness as well as the path to the creation of personal and career development for the employees. This report is aimed at discussing the employee engagement as one of the contemporary issues in the international human resource. Employee engagement is a necessary strategy for an organisation to create competitive advantage in the business world arena. According to Macey & Schneider (2008), employee engagement is a never ending process. He goes to say that the key ingredients for employee engagement is provision of an enabling environment to the employees, which gives them emotional and meaningful enriching experience. He further asserts that the employee engagement is not about keeping the employee happy and rewarding them for the tasks that they have done. It is much deeper than this (Macey, & Schneider, 2008). According to Kahn (1990), employees use different emotional, physical and cognitive levels or abilities in their work performances daily. From the HR perspective today, the employee engagement continues to be of critical consideration in the business world today. Due the challenging economic climate, most organisations now more than ever before have decided to restructure and re-size, which has resulted in the organisations investing in the new approaches to human resources management in order to maintain and

Finite element method Essay Example | Topics and Well Written Essays - 1250 words

Finite element method - Essay Example In order to avoid this situation; one must work in SI units (David, 2006). The Finite Element Method refers to a process of approximating a structure while considering that a structural analysis is being conducted, and existence of several potential sources of error. Major sources of errors include: several simplifications in structure model, element order, loads and boundary conditions, numerical, examples of errors from simplified representation, and general warning (David, 2006). Referred as disfeaturing, this simplification process usually involves taking out small details. It works well when stressed on the areas where omitted details are low. It is crucial to consider that sharp radii can increase the stress to a great extent. Ideally, its expected to start with a simple representation of the actual component and analysing if it is working as expected. If it is turning out as expected, more details can be added at every stage. With every repeat analysis, further details are added. In this way, it is possible to gain appreciation of the details that needs to be incorporate (David, 2006). All components have fixed radii at edges. However, a common perception should be ignored that small radii make "sharp" corner. It may not influence an exterior corner, however, for a sharp re-entrant, corner end up in a stress singularity. In stress singularity refinement of the FEA mesh will result in increased stress values with reduction in element size. Stress results are not requires while displacement results may work, however, a rational approximation of the radius should be utilized in the model. In order to avoid this issue, model components can be made with a substance that can identify plastic bend, however, the pressure at the sharp re-entrant will continue to be unlimited. If stressors are not required, induction of a sharp re-entrant will not influence the results and simplification process will lead to simplify model, for instance,

Speculative Development Project Assignment Example | Topics and Well Written Essays - 5000 words

Speculative Development Project - Assignment Example At a distance it seems fine but there were the run of flats which were interrupted on the east side and a massive portico is provided which faces the axis of Brunswick Square. Theo Crosby, writing an appraisal in the Architectural Review, remarked on the massive portico facing the axis of Brunswick Square. In the evening light the tall thin columns stand out against the chiaroscuro background. This feature focuses more on open space rather enticing potential users from Russell Square station. There are two proposals: Turn the Brunswick into an office space or into residential apartments. If the Brunswick was to be converted into office space it will greatly enhance the environment in the public realm. The estimated cost of the project would be about 22 million. If we were to covert the Brunswick into office space the aim would be to: The Brunswick is a grade II listed building situated in the heart of the Bloomsbury conservation. It is in the area between Bernard Street to the south, Brunswick Square to the east, Handel street to the north and Marchmont Street to the west. The goal of the project would be to honor the building's original intention while at the same time producing an environment that would bring about a newly energetic commercial life into the area. Residential Space If we were to convert the Brunswick into an residential area the express aim would be to "respect the needs of the local residents and business people but still retain the building's original architecture. Originally the Brunswick was to be a low rise development-a blending of the urban housing, shops and offices that would have provided a link between Bloomsbury square and the streets. Due to the economic climate the building was never completed to its original goals, as a result long leases held by residents of the area were sold to the London Borough of Camden to provide low-income public housing. Feasibility of Residential Space Residents of the area has seen The Brunswick's potential, as a result many have already started to buy property. The flats have been snapped up. The flats have doubled in price over the last couple of years- a

The Interpretation of Dreams Essay Example for Free

The Interpretation of Dreams Essay Sigmund Freud was born in 1856 and died in 1939. He was an Austrian psychologist who marked the beginning of a modern psychology by providing the first well-organized explanation of the inner mental forces determining human behaviour. Sigmund Freud is universally considered the father of psychoanalysis and many date the birth of pychoanalystic theory from the 1899 publication of The Interpretation of Dreams ; which sold a minimal number of copies and received a number of copies and received a number of mixed reviews. The book introduces Freud? Theory of the unconscious with respect to dream interpretation and also first discusses what would later become the theory of the â€Å"Oedipus Complex†. Throughout the book, Freyd analyzes his own dreams as examples to prove his new theory of the psychology of dreams. He posits that all dreams represented the fulfillment of a wish on the part of the dreamer and nightmares are expressions of unconscious desires. â€Å"[ ] every dream turns out to be meaningful, psychical formation which can be given an identifiable place in what goes on within our walking life [ † He considered the interpretation of the dream an unexplored science which only Aristotle had investigated about in his book: On dreams and dream interpretation. Freud asserts that, contrary to the reigning scientific opinion, he will prove that is possible to interpret dreams using a scientific method. Freud makes an important distinction between the conscious and the unconscious mind: The conscious mind includes everything that we are aware of. This is the aspect of our mental processing that we can think and talk about rationally. A part of this includes our memory, which is not always part of consciousness but can be retrieved easily at any time and brought into our awareness. The unconscious mind contains our biologically based instincts fot the primitive urges for sex and agression. It con ins all sorts of significant and disturbing material which we need to keep out of awareness because they are too threatening to acknowledge fully. There is another type that is; the subconscious mind which contains thoughts and feelings that a person is not currently aware of, but which can easily be brought to consciousness. It exists just below the level of consciousness before the unconscious mind. This is what we mean in our everyday usage of the world avaliable memory. Freud applied these systems to his structure of the personality, or psyche – the id,ego and superego. Freud also regarded the mind to be like an iceberg, where the greatest part is hidden beneath the water or unconscious.

Why Aristotle Sees Moral Virtue

Why Aristotle Sees Moral Virtue Aristotle claims we become just by doing just acts, temperate by doing temperate acts, brave by doing brave acts. (p120). How does he establish this, and what does it tell us about virtue, and the goal of human life. In this paper I will make discuss why Aristotle sees moral virtue as something which must be taught through emulation of role models, rather than learnt through detached methods. I will then extrapolate what Aristotles claim tells us about moral virtue, and what this means for the goal of a human life. Before I begin to determine what Aristotles claim tells us about virtue, and means for the goal of human life, I will reconstruct how Aristotle arrives at his conclusion. In Book II, chapter I Aristotle begins by defining exactly what he believes virtue to be. Aristotle sees virtue as, being of two kinds, intellectual and moral, intellectual virtue in the main owes both its birth and its growth to teaching (for which reason it requires experience and time), while moral virtue comes about as a result of habit (Aristotle 120). Essentially Aristotle is of the opinion that we are taught intellectual virtue, and we are habituated through repeated exposure to displays of moral virtue by moral role models. Aristotle next contends that moral virtues are not imbedded in us naturally, noting, nothing that exists by nature can form a habit contrary to its nature (Aristotle 120). Aristotle claims that we are constituted by nature to receive moral virtues, but that their full development in us is due to habit. Essentially, we are not born with moral virtue, but it is natural for us to become moral through the emulation of the morality of others. Aristotle moves on to propose the crux of his views on moral virtue, that we develop moral virtues by observing others, and then practicing them. In order to convince the reader of this, he introduces the analogy of the Arts in order to make his case for moral virtue, using the two examples of building and lyre-playing. For things that we have to learn by doing, he says, we learn by doing. Aristotle then delivers his argument that, men become builders by building and lyre players by playing the lyre ; so too we become just by doing just acts, temperate by doing temperate acts, brave by doing brave acts (Aristotle 120). Aristotle offers support for this view by introducing the example of legislation in the contemporary Greek city-states. Aristotle argues that legislators make their citizens good by habituation, which he feels should be the intention of every legislator. Those who do not carry out this habituation of their citizens fail in their goals. Essentially, Aristotle feels that under a good constitution, legislators pass laws that habituate the citizens to behave morally. According to Aristotle, this is what makes the difference between a good constitution and a bad one. Aristotle further purports that like activities produce like dispositions. As a result, he feels that we must give our activities a certain quality, as it is the characteristics of the activity that determine the resulting dispositions. Aristotle expresses this sentiment by claiming that, it is from playing the lyre that both good and bad lyre-players are produced (Aristotle 121). It is essential that good habits be instilled in a person from early youth, he claims, so it is a matter of great importance what sort of habits we form from the earliest age. Aristotle goes as far as to say that, it makes a very great difference, or rather all the difference in the world (Aristotle 121). I will now move on to a discussion of what Aristotles declaration tells us about virtue, and what it suggests that the goal of human life be. Aristotle tells us that virtues cannot be passions, because we are not praised or blamed for the way we feel, but instead are praised or blamed for our virtues this is because our feelings arise more or less involuntarily in response to circumstances (Aristotle 123). Aristotles reason for denying that virtues are faculties is similar. Part of a persons faculties consist of his or her ability to feel anger, however, we do not praise or blame people for having the ability to feel anger instead we often praise people for tending to manifest their ability to feel anger when, and only when, the circumstances call for it (Aristotle 123). Aristotle concludes that virtues must therefore be states of character. By understanding that moral virtues are states of character, Aristotle presents us with a picture of what virtues are. Aristotle tells us that moral virtues are states of character lying at the mean between extremes of excess and deficiency. The view that virtues lie at the mean between the two extremes is intended to help us identify which states of character are the virtuous ones. Both excess and deficiency in the practice of a virtue can result in its destruction while the practice of the mean between them can preserve it. The virtuous state of character will therefore be a tendency to feel and react to circumstances in an appropriate manner and to an appropriate degree (Aristotle 126). Aristotle however, does not tell us just what circumstances warrant what degree of passion with respect to virtues, or what degree of action is appropriate under which circumstances. Common sense suggests that there should be some leeway for judging the deviation from the mean towards excess or def iciency, and that our behaviour must be suited to the particular circumstances as best we see fit given our understanding of intellectual virtue. Not all states of character can be construed as virtuous however. Aristotle notes that there are acts and characteristics that are truly evil and have no intermediate degrees. Aristotle expresses this by declaring that, every action or feeling admits of a mean; because some have names that directly connote depravity, such as malice, shamelessness and envy, and among actions adultery, theft and murder (Aristotle 125). Aristotles theory of moral virtue contends that our ultimate purpose or goal in life should be to reach eudaimonia, the state of moral happiness. However, to reach this state of happiness requires the ability to function according to both our virtues and our sense of innate reason. By using principles of both the intellectual and moral virtue, which becomes habit upon practice and imitation, we must learn to make decisions that are right and just-not necessarily for our own personal benefit, but simply because we possess an understanding that something is the right course of action. Without having these two aspects of morality work together, obtainment of eudaimonia is impossible. In summary, it is our understanding of intellectual virtue (which we learn from others) that allows us to perceive what is right while our display of moral virtue aids us in carrying out what we know to be the correct and just course of action. One of the most important ideas which Aristotle expresses in his Nicomachean Ethics is the need to strike a balance between extremes in behaviour, thought, and action. In his attempt to explain moral virtue and, eudaimonia which is the central goal of human life Aristotle describes the importance of finding a middle ground in ones life or, achieving a balance. To achieve these aims and reach eudaimonia, Aristotle declares that we must do the right thing because it is right, not because there is a personal stake in terms of the future possibility of pleasure or pain (Aristotle 126-127). Essentially, what is morally right or wrong is something that we can understand through intellectual virtue, and we can apply this knowledge of moral behaviour through our practice and habituation of moral virtues. In conclusion, Aristotle arrives at his claim that we become just by doing just acts, temperate by doing temperate acts, brave by doing brave acts by offering an analogy of the Arts. By utilizing the example of a lyre-player, Aristotle shows that one can only become proficient in their actions, including the expression of moral virtues, by observing others actions and then practicing. Moral virtues, for Aristotle, are to be distinguished from intellectual virtues. Moral virtue has to do with feeling, choosing, and acting well. Intellectual virtue is identified as a kind of wisdom acquired by teaching. Aristotle is vehement in his belief that moral virtues are not imbedded in us naturally and that we must acquire them by habituation that this acquisition come during early childhood is of extreme importance in his mind. Aristotle tells us that moral virtue is displayed as the intermediate condition between excess and deficiency with respect to a persons feelings and actions. According Aristotles theory of moral virtue, the goal of human life should therefore be to achieve eudaimonia, which can be acquired by an intellectual understanding of what is right and wrong, and the striking of a balance between extremes in behaviour, thought, and action.

Sociological Methods Of Research

Sociological Methods Of Research Sociology studies the social structures and influences society has on people, their experiences and interpretations of the world around them. Sociology provides information on how human societies are constructed, where our belief system may stem from, our daily routines and how social identities are formed. This essay will cover a small fraction of sociology; Quantitative and Qualitative methodology, its advantages and limitations. What will also be covered is quantitative approach to suicide by Emile Durkheim (1897) and his critic, J.D Douglas qualitative approach to suicide. (Tutor2U 2010) Emile Durkheim (1938) advocated Comtes methodology and agreed that social factors should be studied rather than what goes on internally; his rule was to consider social facts as things, he believed social facts make individuals behave in a certain ways (Haralambous). Sociologists use different methodologies to reach their conclusion; ways of producing and analyzing data so the theories can be tested which are then accepted or rejected. Durkheim adopted the methods of natural science by applying the use of quantitative methods in his suicide study. There are two ways in conducting a research, primary and secondary research. Primary research is where sociologist has to start from scratch as there is no data available, for it to be taken from. In order to do this the researcher needs to design they method of collecting data and analyze the results. Primary research is only validated if the research gives true measurement, descriptions or explanation of what was being studied. Unfortunately there is a likely hood that these finding may not be actually explain peoples everyday settings or actions. (Haralambous p815-16) Secondary research is data that has already been produced by a previous researcher(s); Organizations such as companies, charities, trade unions are useful sources of data as well as documents such as letters, autobiographies and dairies. Secondary research may not be specific enough for researchers needs which in that case means they may have to look at more than one source to come to a conclusion and not only that but more than necessary time is taken up, also information given by the secondary data are sometimes questionable which is why the research has to be aware of this disadvantage (Haralambous 838-9) Quantitative research, in sociology, contains measurements of variables within society; people and groups. In order to get peoples opinions, a survey may be carried out; fieldwork, experiments or documentary research. When these methods are carried out, the researchers are usually avoiding being biased. In order to be unbiased as possible questions that are asked in a closed question form, so the participants replies are very limited or generalised observations are then conducted. Researchers who carrying out quantitative research do not want to get distracted from the intent of the research; they know exactly what they are looking for so their researches are controlled, with closed questions or only statistical information (McGuigan 2010). Alternatively, qualitative research, in sociology, attempts to gather more in depth understanding of individuals or groups actions in the context of social life (Giddens 2009). There usually is no scientific evidence and if there is, its very little evidence. When using qualitative methods of research the investigator is more interested in deeper truths; they prefer to observe things in their natural settings, make sense of things and interpret the information gained; in order to gain information they may interview people or observe them in non artificial settings. Qualitative is more theoretical rather than statistical. Information gained explores deeper into their interest and then data is collected by either observing or interviewing and from the data gain helps generate a hypothesis. Qualitative research digs deeper into reasons of why people may act the way they do. A survey is a method used by researchers to gather information from a sample of individuals whether its from a certain gender, age, race etc where the researchers interest is at and changes depending on the purpose of the study. These samples of individuals are questioned on their information that will help the sociologist conclude, questions can be very much closed questions or open, they are sent out to participants or administered directly; surveys can have a variety of purposes and questions are asked in standardized procedures so the same questions are asked; Surveys help obtain a composite profile of the population. In all reputable survey organizations, organisers should present their results anonymously (Scheuren). Surveys are an advantage for generalizing a big group by getting smaller groups to answer the questions once there is an efficient amount of results. Unfortunately there is a risk of answers to the questions being answered falsely, may not actually reflect their tr ue feelings or may even seem superficial. Surveys can be used to either get quantitative or qualitative data, solely relies on the wording of the question, whether its a open question or a closed question. Field work is when the investigator hangs out, works or lives with a group, organization or community and lives the realism of the environment by taking direct part in their activities; in other words real world experience. Investigators who take part in this are likely to have a better understanding of those who actually are a part of what they are investigating. This method is more likely to be used to have a qualitative outcome. There are two types of experiments, one being laboratory and the other being field experiment. Experiments are used to test the hypothesis and the relationships between the two variables are tested. It is conducted in a controlled environment where the variables are isolated and the correlation between things can be discovered. In sociology laboratory experiments are barely used as they believed variables cannot be controlled, the environment people are put in are artificial which will lead to the actions of people being artificial too and they do not believe its right to put laboratories just to measure the effect of variables. Field experiments have been proved to be more used and affective in sociology as they are conducted in normal everyday situations and environments; variables cannot be controlled. Although field experiments arent conducted in laboratory they are still not exact but are more valid than lab experiments as the actions from the people are real; less artificial. B ut if people are aware that they are taking part in a experiment their actions can become artificial, for an example workers may work harder in normal conditions because they know they are being observed. Emile Durkheim (1897) did a socially confusing study on suicide based on the hypothesis; as the individuals social unity decreased it was found there was an increase of suicide rates. Durkheim (1897) did not believe that reasoning for suicide was an individual act, he believed suicide was a social fact that can be proved by other social facts; the larger social forces can account for social facts. Durkheim (1897) employed quantitative research to his study of suicide, to make it have a scientific backbone as he believed it to be more rich and valid, by examining the official suicide statistics in France; these official statistics were secondary sources produced by the government. He believed that patterns of suicide were linked to the way which individuals were integrated and regulated by society and how they controlled them, he identified there were four types of suicide, and he generalized these four types of suicide to everyone; the four were Egoistic, Anomic, Altruistic and Fatal istic suicide. Egoistic suicide is when an individual is isolated or their ties to a group is broken or weakened; Catholics and Protestants. Anomic suicide is when an individual feels his life has a lack of meaning and feels as they are worthless, this can be a result of a divorce. Altruistic suicide is when an individual values others more for an example a mother who pushes their child out the way of a oncoming car and hurts herself or a suicide bomber. Fatalistic suicide is when an individual feels hopeless about their fate or feels excessively restraint for an example an individual may take their own life before the police arrest them to avoid being in a cell for the rest of their life or many years. Egotistic and Anomic are the two most common occurred, of the four. In contrast to Durkheims study of suicide Douglas (1967) is one of the many interpretive sociologists; interpretive approach strongly advocate qualitative data as they believe sociologists should be able to understand and interpret the meanings and motives of actions and quantitative data does not help discover meanings and motives. Interpretative sociologists reject studying social facts as things, they say natural sciences deal with matter and matter does not have a mind which in that case has no consciousness which in that case there is no meaning in behaviour. Interpretive approach acknowledges that people have consciousness, it is believed that people will interpret the meaning of a stimulus and then react to it; meaning is attached to the stimulus. J.D Douglas (1967) conducted his study Social meanings of Suicide, he believed that the official statistics were systematically biased and could have been made up by friends, families, and coroners. He disputed that Durkheim (YEAR) neglected other meanings attached to why an individual may commit suicide, he believed it to be wrong that Durkheim (YEAR) would treat all suicides the same without investigating other reasonings. Douglas was concerned with meanings of suicide and believed there to be different reasons behind a suicide than the four generalisations Durkheim (YEAR) had made. In Douglass (1967) study of social meanings for suicide he believed there to be four different meanings of suicide. Douglas (1967) believed in qualitative research methods to find his answers to why an individual would commit suicide; his methods were conducting case studies, unstructured interviews and diaries, from his investigations he found four types of suicide, the four are Transformation of the s oul, this is where it is used as a way of getting into heaven, transformation of self, this is where the individual would want others to think differently of them, suicide where an individual wants sympathy and suicide where the individual tries to get revenge by leaving the other person feeling guilty.

Destiny, Fate, and Free Will in Oedipus the King - A Victim of Fate :: Oedipus Rex Essays

Oedipus the King as a Victim of Fate Among the first thing a historian discovers in his study of early civilization are records of people's belief, or faith, in powers greater than themselves, and their desire to understand what causes these powers to act. People everywhere wonder about the marvelous things in the sky and on the earth. What makes the rain? How do the plants and animals live and grow and die? Why are some people lucky and others unlucky? Some believe in free will while others believe in fate or destiny. In the play Oedipus the King by Sophocles, Oedipus was a true victim of fate. Gods and goddesses were believed to be responsible for the wonders of science, and the vagaries of human nature; therefore, according to the facts of this story, Oedipus was a true victim of fate for several reasons. Laius and Jocasta, the childless king and queen of Thebes, were told by the god Apollo that their son would kill his father and marry his mother (page 56). A son was born to them, and they tried to make sure that the prophecy would not come true. They drove a metal pin through the infants ankles and gave it to a shepherd, with instructions to leave it to die. The shepherd pitied the little infant so he gave the child to another shepherd. This shepherd gave the baby to a childless king and queen of Corinth, Polybus and Merope. This royal couple named the boy Oedipus, which in its Greek form Oidipous means "swollen foot." Oedipus was brought up believing that Polybus and Merope were his real parents, and Lauis and Jocasta believed that their child was dead and the prophecy of Apollo was false. Many years later, he was told by a drunk man at a banquet that he was not a true heir of Polybus (page 55). He then went to the oracle of Apollo, to ask the god who his real parents were. All he was told was that he would kill his father and marry his mother (page 56). He resolved never to return to Corinth, to Polybus and Merope, and started out to make a new life for

Satire and Fantasy in Kurt Vonneguts Cats Cradle Essay -- Kurt Vonne

Satire and Fantasy in Kurt Vonnegut's Cat's Cradle For this essay, I decided to pick two terms that describe Cat's Cradle. I felt that satire and fantasy were two terms that suited the novel quite well. The book qualifies as a satire because it makes a mockery of things that were of concern in the sixties. For example, the Cuban missile crisis was a big issue in the early sixties. Religion was taken much more seriously, and the family unit was more tightly wound. In the novel, the threat comes not from a large warhead, but from a small crystal of Ice-nine. Religion is satired in Bokononism, which is a religion that is based on lies. The family unit is satired by the Hoenikkers. The father is detached from reality, the sister is a giant, and the brother is a midget. The Cuban threat is also satirized by San Lorenzo and it's dictator Papa Monzano. Cat's Cradle also has many elements of fantasy woven throughout. A small crystal that can freeze water and can destroy the world and can only be stopped by a temperature of 114 degrees is a good example of the fantasy element in the novel. It gives the story an almost futuristic feel, even though by modern standards the book is dated. Jonah's whole adventure is reminiscent of mythological tales. He journeys to a far away land, San Lorenzo. He is called to adventure by Newt's letter. He finds a mystical talisman, Ice-nine. He falls in love with the beautiful maiden, Mona. The religion of Bokononism has a fantasy element to it. Johnson changes his name to Bokonon much like in Buddhism. There are all the writings in the Books of Bokonon, and the Boko-maru which are both fantastic ideas in themselves. Cat's Cradle contains many elements of many types of genres. It could be consider... ...t has no real motivation, and why should he when he is going to be taken care of by Angela for the rest of his life. I like Newt because he does not feel sorry for himself, and treats everything matter-of-factly and as if it is obvious, "Isn't everybody [self-taught]?" Newt appears to be a person who does not care what everyone else thinks and always strives to be an individual. I think that the satire alone in Cat's Cradle is enough to encourage humanity to make a better world. Vonnegut makes things seem funny in the book that really are not funny in real life, such as an atom bomb, a father who ignores his child and everyone else, and an island where people are hung for practicing a certain religion. The book is amusing, but it made me think about what the world would be like if it really was that way. It would be horrible, and definitely nothing to laugh at.

Hank Kolb Case Study Essay

Quality, or lack of, is the result of many decisions made by many people over a long period of time. The Hank Kolb case quality problems all point to one fundamental problem, management. There are four special cause variations in a quality process: man, machine, materials and method. The Hank Kolb case has issues in each of these four fields and this case analysis will examine the issues within the four cause variations and show how they all point to management as the main perpetrator of poor quality. Recommendations, both short and long term approaches, will be outlined to help management create a quality product and work environment in each of the four fields. The â€Å"man† root cause of poor quality is seen in the lack of training and poor attitudes of workers. Training is not a prerequisite to individuals moving into new positions. This creates under-qualified people in skilled labor roles. The attitude of the workers considers quality as a topic that burdens and impedes people from doing their jobs. Issues with the â€Å"machine† aspect are an improper maintenance process and the machine used for something it is not designed to do. With no scheduled preventative maintenance, nonstandard downtime was running at 15% of actual running time and repairs had been made twice a month for the last six months. Keeping the machinery in top-running condition has not been a priority and its’ effects have been felt down the line with over-pressurized cans. The plastic nozzle heads were often found with burrs on the inside rim. This forced the company to increase the application pressure at the filling head to solve this problem. Quality is being affected within the â€Å"materials† variable. Finally, there are numerous problems identified within the â€Å"methods† cause variation. There is lack of policy and procedure. Examples of this are completing inspections after the fact and not having any feed-back loops. Not having equipment maintenance records is another example of the lack of methods that have added to the overall lack of quality. These four special cause variations can be visualized in a fishbone diagram (appendix 1) to show the cause/ effect relations of quality problems. Each special cause variation points to poor management as the fundamental problem in this case. This is exacerbated as the company puts market share and schedule above quality and safety. To create a solution to the quality problem, Hank will need to first deal with managerial support and attitude. Hank should create a company-wide quality policy that is actively backed by senior management. Then, a training program should be initiated for all skilled labor and supervisory positions. Next, start collecting data on how and why the machinery is breaking down. Soon after, Hank should do a cost benefit analysis to see if upgrading the machinery will boost production of the Greasex product. Hank needs to be aggressive with the nozzle supplier to demand greater quality. Finally, all policies and procedures will need to be created and implemented with quality at the forefront of every concept.

Time to Digital Converter Used in All Digital Pll

Master Thesis ICT Time to Digital Converter used in ALL digital PLL Master of Science Thesis In System-on-Chip Design By Chen Yao Stockholm, 08, 2011 Supervisor: Dr. Fredrik Jonsson and Dr. Jian Chen Examiner: Prof. Li-Rong Zheng Master Thesis TRITA-ICT-EX-2011:212 1 ACKNOWLEDGEMENTS I would like to thank: Professor Li-Rong Zheng for giving me the opportunity to do my master thesis project in IPACK group at KTH. Dr. Fredrik Jonsson for providing me with the interesting topic and guiding me for the overall research and plan. Dr.Jian Chen for answering all my questions and making the completion of the project possible. Geng Yang, Liang Rong, Jue Shen, Xiao-Hong Sun in IPACK group for the discussion and valuable suggestions during the thesis work. My mother Xiu-Yun Zheng and my husband Ming-Li Cui for always supporting and encouraging me. i ABSTRACT This thesis proposes and demonstrates Time to Digital Converters (TDC) with high resolution realized in 65-nm digital CMOS. It is used as a phase detector in all digital PLL working with 5GHz DCO and 20MHz reference input for radio transmitters.Two kinds of high resolution TDC are designed on schematic level including Vernier TDC and parallel TDC. The Sensed Amplifier Flip Flop (SAFF) is implemented with less than 1ps sampling window to avoid metastability. The current starved delay elements are adopted in the TDC and the conversion resolution is equal to the difference of the delay time from these delay elements. Furthermore, the parallel TDC is realized on layout and finally achieves the resolution of 3ps meanwhile it consumes average power 442 µW with 1. 2V power supply. Measured integral nonlinearity and differential nonlinearity are 0. LSB and 0. 33LSB respectively. Keywords: All Digital PLL, Time to Digital Converter (TDC), Sensed Amplifier Flip Flop (SAFF), Current Starved, Vernier delay line ii Contents ACKNOWLEDGEMENTS †¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦. i LIST OF FIGURES†¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦.. iv LIST OF TABLES †¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦. 1. 2. Introduction †¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚ ¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦. 1 State of art †¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦ 4 2. 1 2. 2 2. 3 2. 4 3 Buffer delay line TDC†¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦.. 4 Inverter delay line TDC †¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦.. Vernier TDC †¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦. 5 Gated ring oscillator (GRO) TDC †¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦.. 6 System level design †¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦. 7 3. 1 3. 2 3. 3 3. 4 Goal †¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦ Vernier delay line TDC †¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦ 9 Parallel TDC †¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦.. 10 Performance comparison †¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦.. 11 4 Schematic design and simulation †¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦ 12 4. 1 Sense Amplifier Based Flip-Flop â € ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦. 2 Schematic design†¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦ 14 Sampling window simulation †¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦.. 16 4. 1. 1 4. 1. 2 4. 2 Vernier delay line TDC †¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦. 21 Delay cells †¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦ 21 Simulation results †¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦.. 5 4. 2. 1 4. 2. 2 4. 3 Parallel TDC †¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦.. †¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦ 28 Delay cells †¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦ 28 Simulation results †¦Ã¢â‚¬ ¦Ã¢â ‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦.. 30 4. 3. 1 4. 3. 2 5 Layout and post-simulation†¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦ 3 5. 1 5. 2 5. 3 Layout of SAFF and post-simulation †¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦.. 33 Layout of parallel TDC and post-simulation †¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦ 35 Comparison and analysis †¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã ¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦.. 38 6 7 8 Conclusion †¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦ 0 Future work †¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦.. 41 Reference †¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦.. 42 iii LIST OF FIGURES Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 Figure 14 Figure 15 Figure 16 Figure 17 Figure 18 Figure 19 Figure 20 Figure 21 Figure 22 Figure 23Figure 24 Figure 25 Figure 26 Figure 27 Figure 28 Figure 29 Figure 30 Figure 31 Figure 32 Figure 33 Figure 34 Figure 35 Figure 36 Figure 37 Figure 38 Figure 39 Figure 40 Figure 41 Figure 42 Figure 43 Figure 44 Figure 45 iv Effect of LO phase noise in transmitter Block diagram of the phase-domain ADPLL frequency synthesizer Retiming of the reference clock signal (FREF) Operating principle of time-to-digital converter Buffer delay line TDC Inverter delay line TDC Vernier delay line TDC Gated ring oscillator TDC Test bench for measuring rising/falling time of input of TDC Input and output of inverter Diagram of Vernier delay line TDC Timing of the interfaces of Vernier TDC Diagram of parallel TDC Timing of the interfaces o f parallel TDC Symmetric SAFF Schematic of SAFF Schematic of Sense Amplifier Schematic of symmetric SR latch Test bench of SAFF Normal Sampling Case Extreme case of sampling for setup time simulation Extreme case of sampling for hold time simulation Sampling window simulation Current starved delay element Schematic of Matched delay cell Schematic of delay cell 1 Schematic of delay cell 2 Schematic of Vernier delay line TDC Input of Vernier TDC (stop – start) = 0ps Input of Vernier TDC (stop – start) = 20ps Vernier TDC transfer function Vernier TDC linearity Monte Carlo simulation of the resolution for Vernier delay line TDC Delay cell in Parallel TDC Delay time Vs width of transistor T5 Schematic of Parallel TDC Input of parallel TDC (stop – start) = 0ps Input of parallel TDC (stop – start) = 20ps Parallel TDC transfer function Parallel TDC linearity Floor Plan of SAFF Layout of SAFF Post-simulation of sampling window Floor plan of Clock distribution Layo ut of parallel TDC Figure 46 Figure 47 Figure 48 Figure 49 Input of parallel TDC after layout (stop – start) = 0ps Input of parallel TDC after layout (stop – start) = 30ps Parallel TDC transfer function after layout Parallel TDC linearity after layout LIST OF TABLES Table 1 Table 2 Performance comparison between Vernier TDC and parallel TDC Comparison to previous work v 1.Introduction All digital phase locked loop (ADPLL) is employed as frequency synthesizer in radio frequency circuits to create a stable yet tunable local oscillator for transmitters and receivers due to its low power consumption and high integration level. It accepts some frequency reference (FREF) input signal of a very stable frequency of and then generates frequency output as commanded by frequency command word (FCW). The desired frequency of output signal is an FCW multiple of the reference frequency. For an ideal oscillator operating at all power is concentrated around , but the spectrum spreads i nto nearby frequencies in practical situation.This spreading is referred as phase noise which can cause interference in adjacent bands in transmitters and reduce selectivity in receivers [1]. Fig. 1. Effect of LO phase noise in transmitter [1] For example, shown as Fig. 1, when a noiseless receiver must detect a weak desired signal at frequency in the presence of a powerful nearby transmitter generating at frequency with substantial phase noise, the desired signal will be corrupted by phase noise tails of transmitter. Thus the modern radio communication systems require strict specifications about phase noise of synthesizers. In the ADPLL, the time to digital converter (TDC) serves as the phase frequency detector (PFD) meanwhile the digitally controlled Oscillator (DCO) replaces the VCO.The core module is DCO which deliberately avoids analog tuning voltage controls. The DCO is similar to a flip flop whose internal is analog but the analog nature does not propagate beyond the boundari es. Compared to the analog PLL, the loop filter can be implemented in a fully digital manner which will save a large amount of area and maintain low power consumption. 1 Fig. 2. Block diagram of the phase-domain ADPLL frequency synthesizer [2] Fig. 2 shows a type II ADPLL which includes two poles at zero frequency. It has better filtering capabilities of oscillator noise compared to type I ADPLL, leading to improvements in the overall phase noise performance. The ariable phase signal is determined by counting the number of rising clock transitions of the DCO oscillator clock. The reference phase signal is obtained by accumulating the Frequency Command Word (FCW) with every rising edge of the retimed Frequency Reference (FREF) clock. The sampled variable phase is subtracted from the reference phase in a synchronous arithmetic phase detector which is defined by = + ? [k] [2]. Fig. 3. Retiming of the reference clock signal (FREF) [3] 2 There are two asynchronous clock domains, FREF and CKV, and it is difficult to compare the two digital phase values physically at different time instances without facing the metastability problem.During frequency acquisition, their edge relationship is not known, and during phase lock, the edges will exhibit rotation if the fractional FCW is nonzero [1]. Therefore, it is imperative that the digital-word phase comparison should be performed in the same clock domain. This is achieved by retiming process which is performed by oversampling the FREF clock with CKV for synchronization purpose (fig. 3). The retimed clock, CKR is used to synchronize the internal ADPLL operations. However, the retiming process generates a fractional phase error in CKV cycles which is estimated by TDC [3]. The DCO produces phase noise at high frequency, while the TDC determines the in band noise floor [4].The noise contribution of TDC within the loop bandwidth at output of ADPLL is where denotes the delay time of a delay cell in the TDC chain, is the period of RF output and is the frequency of the reference clock [1]. The equation above indicates that a smaller leads to smaller quantization noise from TDC. As a result, the effort is devoted to achieve high resolution TDC in order to obtain low phase noise of ADPLL. Fig. 4. Operating principle of time-to-digital converter [5] Fig. 4 illustrates the principle of time-to-digital converter based on digital delay line. The start signal is delayed by delay elements and sampled by the arrival of the rising edge of stop signal.The sampling process which can be implemented by flip-flops freezes the state of delay line as the stop signal occurs. The outputs of flip-flop will be high value if the start signal passes the delay stages and the sampling process will generate low value if the delay stages have not been passed by start signal. As a result, the position of high to low transition in this thermometer code indicates how far the start signal can be propagated in the interval spanned by star t and stop signal. 3 2. State of art 2. 1 Buffer delay line TDC Fig. 5. Buffer delay line TDC [5] The start signal ripples along the buffer chain and flip-flops are connected to the outputs of buffers. On the arrival of stop signal the state of delay line is sampled by flip-flops.One of the obvious advantages of this TDC is that it can be implemented fully digital. Thus it is simple and compact. However, the resolution is relatively low since it is the delay of one buffer. 2. 2 Inverter delay line TDC Fig. 6. Inverter delay line TDC [5] The resolution in this TDC is the delay of one inverter which is doubled compared to buffers delay chain. In this case, the length of measurement intervals is not indicated by the position of high to low transition but by a phase change of the alternation of high to low sequence. Consequently, the rise and fall delay of inverter should be made equal which requires highly 4 match of the process.In addition, the resolution is still limited by technolog y and therefore not high enough in our application of ADPLL. 2. 3 Vernier TDC Fig. 7. Vernier delay line TDC [6] Vernier delay line TDC is capable of measuring time interval with sub-gate resolution. It consists of two delay lines which delay both start signal and stop signal. The delay in the first line is slightly larger than the delay in the second line. During the measurement, the start signal propagates along the first line and the stop signal occurs later. It seems like the stop signal is chasing start signal. In each stage, it catches up by = Delay1- Delay2 Therefore the resolution is dependent on the difference of two delay stages instead of one delay element.Although the Vernier delay line TDC improves the resolution effectively, the area and power consumption is increased dramatically as the dynamic range becomes larger due to that each stage costs two buffers and one flip-flop. Besides, the conversion time will be increased and in a result it might be not feasible to work in a system. 5 2. 4 Gated ring oscillator (GRO) TDC Fig. 8. Gated ring oscillator TDC [6] The GRO TDC could achieve large dynamic range with small number of delay elements. It measures the number of delay element transitions during measurement interval. By preserving the oscillator state at the end of the measurement interval [k? ], the quantization error [k? 1], from that measurement is also preserved. In fact, when the following measurement of [k? 1] is initiated, the previous quantization error is carried over as [k] = [k? 1]. This results in first-order noise shaping of the quantization error in the frequency domain. Apart from the quantization noise, according to the well-known barrel shift algorithm for dynamic element matching, GRO TDC structure realizes first order shaping of mismatch error [6]. Thus, we can expect that this architecture ideally achieve high resolution without calibration even in the presence of large mismatch. 6 3 System level design 3. 1 GoalThe proposed TDC is designed to work with a 5GHz DCO and a 20MHz reference input while the circuit is fabricated in 65nm IBM CMOS technology; the supply voltage is 1. 2V and development environment is Cadence 6. 1. 3. Fig. 9. Test bench for measuring rising/falling time of input of TDC In order to find out the rising/falling time of the input signal for TDC, the 5GHz sine wave signal which is the same as the output of DCO in ADPLL is put through the inverter with the smallest size and the rising/falling time of the output of inverter is measured (Fig. 9) . 7 Fig. 10. Input and output of inverter Rising/falling time = 16. 58ps. This value is applied to model the practical case of input signals for TDC.The purpose for putting the sinusoid signal generated from DCO passing through the smallest inverter is to model the worst case for TDC with weakest driving ability. As the system level simulation result of ADPLL presents, the dynamic range of TDC is 20ps. The converter resolution is required to be around 2ps meanwhile the power consumption should be kept as low as possible. Since in the application of this ADPLL, sub-gate resolution and small dynamic range are targeted, two kinds of topologies of TDC are proposed. One is Vernier delay line TDC and the other one is parallel TDC. The comparison of these two architectures is concluded and both of them are designed on schematic level. 8 3. 2 Vernier delay line TDCStart Matched delay cell1 EN EN_ Delay1 Delay1 Delay1 Start_ Matched delay cell1 D Q D_ CLK Delay1 D Q0 D_ CLK Delay1 Delay1 D Q26 D_ CLK Stop Fig. 11. Diagram of Vernier delay line TDC 200ps Matched delay cell2 Delay2 Delay2 Delay2 start 20ps stop enable Valid output 2ns TDC_output Fig. 12. Timing of the interfaces of Vernier TDC As the description about Vernier TDC before, the start signal and stop signal are propagated by two delay line with small delay difference each stage respectively. The clock gating technology controlled by enable signal is used to realize low p ower dissipation. The timing relationship of interfaces is described in Fig. 2 which indicates that enable signal should be set to high value half 9 cycle of start signal ahead of the stop rising edge and the conversion time is about 2ns. The delay time of each stage in TDC is about 60ps to 70ps and 27 stages are design to cover the whole dynamic range so that the conservative estimation of conversion time of TDC would be no more than 2ns. The next stage of TDC in ADPLL should sample the output when it is stable. Since the period of FREF is 50ns which means that the instance of measurement occur every 50ns, it is reasonable to adopt the method of serial conversion and prepare the valid output data after 2ns delay. 3. 3Parallel TDC Start Current Staved delay cell EN EN_ Start_ Current Starved delay cell D Q0 D_ CLK Stop Fig. 13. Diagram of parallel TDC Delay1 Delay2 Delay12 D Q1 D_ CLK D Q11 D_ CLK 10 200ps 20ps start stop enable Valid output 420ps TDC_output Fig. 14. Timing of the i nterfaces of parallel TDC Configuring the gates not in a chain but in parallel generates TDC depicted in Fig. 13. The start signal applied to all delay elements in parallel. On the rising of stop signal the outputs of all delay elements are sampled at the same time. Instead of propagating the differential start signal, stop signal is delayed to avoid differential mismatch problem.The delay cells connected to stop signal are sized for delays = 0+? ?N =? . The time difference between the delayed stop signal is quantized with a resolution The conversion results are available immediately after the rising of stop signal. 3. 4 Performance comparison Parallel TDC Parallel delay elements with gradually increasing propagation delays are simultaneously sampled on the arrival of stop signal. No loop structure feasible Sub-gate resolution Conversion time independent from resolution Susceptible to variations Not feasible to high dynamic range Careful layout design Vernier TDC Principle Start and stop signals propagate along two delay lines with slightly different delays.Loop structure Pros Loop structure possible Sub-gate resolution Modular structure High dynamic range possible with loop structure Differential delay lines Conversion time depends on measurement interval and resolution Cons Table1. Performance comparison between Vernier TDC and parallel TDC 11 4 Schematic design and simulation 4. 1 Sense Amplifier Based Flip-Flop Flip-Flops are critical to the performance of Time to Digital Converter due to the tight timing constraints and low power requirements. Metastability is a physical phenomenon that limits the performance of comparators and digital sampling elements, such as latches and flip-flops. It recognizes that it akes a nonzero amount of time from the start of a sampling event to determine the input level or state [15]. This resolution time gets exponentially larger if the input state change gets close to the sampling event. In the limit, if the input changes a t exactly the same time as the sampling event, it might theoretically take an infinite amount of time to resolve. During this time, the output can dwell in an illegal digital state somewhere between zero and one. However, this flip flop is supposed to be reused in ADPLL so that the metastable condition of the retimed reference clock CKR is not acceptable. One reason is that the metastability of any clock could introduce glitches and double clocking in the digital logic circuitry being driven.The other reason is that it is quite likely that within a certain metastability window between FREF and CKV, the clock to Q delay of the flip flop would have the potential to make CKR span multiple DCO clock periods. This amount of uncertainty is not acceptable for proper system operation [4]. For the application of TDC, due to that the metastability sampling window should be no larger than the high resolution to avoid bubbles in TDC code [7], sensed amplifier based flip-flop (SAFF) is chosen. 1 2 VDD MP1 MP2 MP3 MP4 MN3 VDD MN4 D MN1 MN5 MN2 D_ CLK MN6 Pulse Generator Symmetrical SR latch S_ S R VDD R_ MP7 MP8 MP5 MP6 MP9 Q MP10 Q_ MN9 MN10 MN7 MN11 MN12 MN8 Fig. 15. Symmetric SAFF The SAFF shown as Fig. 5 consists of sense amplifier in the first stage and SR latch in the second stage. The amplifier senses complementary differential inputs and produces monotonous transitions from high to low logic level on one of the outputs following the leading clock edge. The SR latch captures each transition and holds the state until the next leading clock arrives [8]. When CLK is low, S_ and R_ are charged to high level through MP1 and MP4 meanwhile MN6 is closed. If D is high, S_ will be discharged through MN3, MN1 and MN6 which is opened by clock leading edges. Accordingly, R_ is hold to high level and Q is high in this case. The additional transistor MN5 is used to provide the discharging patch to ground. For example, when 13 ata is changed as CLK is high which means D is low and D _ is high at this time, S_ would be charging to high level if there is no MN5. However, S_ could be discharged through MN3, MN5, MN2 and MN6 since MN5 provides another path to ground. Although SR latch is able to lock the state of outputs of sense amplifier, MN5 prevents potential charging caused by leakage current even after the input data is changed and therefore guarantee the stable outputs of flip-flop. The SR latch, as the output stage, is kind of symmetric topology with equivalent pull-up and pulldown transistors network. Q+ = S + R_ ·Q Q_+ = R + S_ ·Q_ In the equations above, Q represents a current sate and Q+ represents a future state after the transition of clock.Thus this circuit has equal delays of outputs and provides identical resolution of the rising and falling meta-stability of their input data. In addition, the data input capacitive loading is only one NMOS transistor and the interconnect capacitance parasitic is minimized. 4. 1. 1 Schematic design The basic pri nciples of the SAFF design are that the size of the input transistors should be small enough to minimize the load effect of SAFF and large enough to ensure the speed of it. The PMOS and NMOS networks should be matched and the sizes of transistors are adjusted to obtain equal delay of differential outputs. Fig. 16. Schematic of SAFF 14 Fig. 17. Schematic of Sense Amplifier Fig. 18. Schematic of symmetric SR latch 15 4. 1. 2 Sampling window simulation Fig. 19.Test bench of SAFF The ideal switch is used to initialize the output signal Q otherwise Q will be floating at the beginning of simulation which would result in unpredictable rising or falling edge at the beginning therefore make it difficult to measure a fixed number of signal transition edge. In the practical case, the initial value of inputs of flip flop is either zero or one. The simulation is performed by tuning the delay time of CLK in order to change the time interval between CLK and D/D_. There are several cases simulated to verify the timing constraints of SAFF including setup timing, hold timing and sample window. 1. Normal sampling 16 Fig. 20. Normal Sampling Case Data D changes from zero to one and then is sampled after it is stable for a while. The crossing point of Q and Q_ is around 600mV which means there are equal delay of clock to Q and clock to Q_ due to the symmetric topology of SAFF. 2.Setup time simulation Setup time is the minimum time prior to triggering edge of the clock pulse up to which the data should be kept stable at flip flop input so that data could be properly sampled. This is due to the input capacitance present at the input. It takes some time to charge to the particular logic level at the input. During the simulation, the input data is changing from low to high and high value is supposed to be sampled. Sweep the position of CLK to find out when SAFF cannot capture the correct data. 17 Fig. 21. Extreme case of sampling for setup time simulation The clock to Q delay is incre asing exponentially when input data is approaching the clock triggering edge.When the data comes later than clock edge for 15ps, the clock to Q delay is up to about 280ps shown in Fig. 21. If the data comes even later than this, the output of flip flop will enter into metastable state or will never output high value. 3. Hold time simulation Hold time is the minimum time after the clock edge up to which the data should be kept stable in order to trigger the flip flop at right voltage level. This is the time taken for the various switching elements to transit from saturation to cut off and vice versa. During the simulation, the input data is changing from high to low and high value is supposed to be sampled. Sweep the position of CLK to find out when SAFF cannot capture the correct data. 18 Fig. 22.Extreme case of sampling for hold time simulation The clock to Q delay is increasing exponentially if transition of input data from one to zero happens close to the clock edge. As long as t he data could keep stable long enough the flip flop is capable of recognizing it during limit time interval. The hold timing constraint is that data should be stable after the clock rising at least 16ps (Fig. 22) to guarantee flip-flop could sample the right value otherwise the flip flop will enter into illegal state or never output high value. 4. Sampling window 19 2. 9 2. 8 2. 7 2. 6 x 10 -10 Tclk-Q 2. 5 setup time 2. 4 2. 3 2. 2 2. 1 2 -0. 5 hold time 0 0. 5 1 1. 5 2 Tdata-clk 2. 5 3 3. 5 x 10 4 -11 Fig. 23. Sampling window simulationSampling window is defined as the time interval in which the flip-flop samples the data value. During the interval any change of data is prohibited in order to ensure robust and reliable operation [8]. The flip-flop delay increases as the signal approaches the point of setup and hold time violation until the flip-flop fails to capture the correct data [9] which is displayed in Fig. 23. Metastability is modeled in critical flip-flops by continuous ins pection of the timing relationship between the data input and clock pins and producing an unknown output on the data output pin if the delay to clock skew falls within the forbidden metastable window. Referring to Fig. 3, the metastable window is defined as an x-axis region such that the clock to Q delay on the y-axis is longer by a certain amount than the nominal clock to Q delay. For example, if the nominal clock to Q delay is 200ps when the data to clock timing is far from critical, the metastability window would be 15ps if one can tolerate clock to Q delay increase by 20ps. If one can tolerate a higher clock to Q delay increase of 30ps, the metastable window would drop to 6 ps. A question could be asked as to how far this window can extend. The limitation lies in the fact that for a tight data to clock skew, the noise or other statistical uncertainty, such as jitter, could arbitrarily resolve the output such that the input data is missed.Therefore, for a conventional definition of setup time, not only must the output be free of any metastable condition, but the input data have to be captured correctly. For this reason, the setup and hold times are conservatively defined in standard-cell libraries for an output delay increase of 10 or 20% over nominal. The specific nature of TDC vector capturing does not require this restrictive constraint. Here, any output-level resolution is satisfactory for proper operation as long as it is not metastable at the time of capture, and consequently, 20 the metastable window could be made arbitrarily small [1]. This SAFF demonstrates very narrow sampling window less than 1ps according to the simulation results. 4. 2Vernier delay line TDC There are several components in Vernier delay line TDC including inverter, SAFF, matched delay cell, delay cell 1 and delay cell 2 in which matched delay cell has the same circuit topology with other two delay cells except that it has enable control pins. 4. 2. 1 Delay cells There are severa l methods to implement delay elements. The most popular three methods for designing variable delay cells are shunt capacitor technique, current starved technique and variable transistor technique [10]. In this thesis project, current starved delay element is employed because of its simple structure and relatively wide delay range of regulation.Vdd VBP M4 M2 M6 Vdd in C M1 M5 out VBN M3 Fig. 24. Current starved delay element As can be seen from the Fig. 24, there are two inverters between input and output of this circuit. The charging and discharging currents of the output capacitance of the first inverter, composed of M1and M2, are controlled by the transistors M3 and M4. Charging and discharging currents depend on the bias voltage of M3 and M4 respectively. In this delay element, both rising and 21 falling edges of input signal can be controlled. By increasing/decreasing the effective on resistance of controlling transistor M3 and M4, the circuit delay can be increased /decreased.F ig. 25. Schematic of Matched delay cell As the enable signal is set to high level, the input signal will pass through this delay cell. The enable signal should be set to high level before the active edge of input signal comes. The differential start signal and stop signal passed through this delay cell to produce matched rising/falling edge signal for the next stage in TDC. With respect to design of the size of transistors, the input transistors of the delay cell should be relatively large to shield the load effect of SAFF meanwhile allow T5 to control the changing and discharging current through the capacitors of the first stage of inverter.The second stage of inverter should have enough driving ability for 5GHz input signals and therefore the sizes are specified large enough to withdraw sufficient current from power supply for transition. Due to that the differential signals are delayed, the delay cell is also required to have matched PMOS and NMOS networks to achieve equal delay time for rising or falling input signals. 22 Fig. 26. Schematic of delay cell 1 Fig. 27. Schematic of delay cell 2 23 The only difference between these two delay cells above is the size of transistor T5. The W/L ratio of T5 in delay cell 2 is a bit larger than delay cell 2 makes the delay of delay cell 2 is slightly shorter than delay cell 1. These two delay cells constitute two delay lines for Vernier TDC. Fig. 28.Schematic of Vernier delay line TDC This Vernier TDC includes 27 stages of delay cells for the reason that it should cover the dynamic range of 20ps and the additional offset value introduced by the setup timing of SAFF. The first dumpy stage of delay cell is used to match the differential input signals for the following delay lines so that the input signals for each stage are characterized with the same rising or falling time. As a result, the delay difference between each delay pair for start and stop signal is only dependent on the different size of transistors in the current starved delay cell. 24 4. 2. 2 Simulation results The input of Vernier TDC, the delay difference between the start and stop signal, is swept from 0 to 20ps.The resolution and linearity are calculated and analyzed by conversion results from TDC. Fig. 29. Input of Vernier TDC (stop – start) = 0ps Fig. 30. Input of Vernier TDC (stop – start) = 20ps 25 The offset value of this TDC is 8 observed from Fig. 29. The result shown in Fig. 30 indicates that the start signal has passed through 22 stages of delay cells as the input is 20ps. Resolution = (20ps – 0ps)/ (22 – 8) = 1. 43ps 25 20 Output of Vernier TDC (ps) 15 10 5 0 0 2 4 6 8 10 12 14 Input of Vernier TDC (ps) 16 18 20 Fig. 31. Vernier TDC transfer function 0. 6 0. 4 0. 2 DNL and INL [LSB] 0 -0. 2 -0. 4 -0. 6 -0. 8 -1 INL DNL 0 2 4 6 8 10 12 Input of Vernier TDC 14 16 18 20 Fig. 32. Vernier TDC linearity 26The Differential Non Linearity (DNL) is the deviation in the difference between two successiv e threshold points from 1LSB. Integral Non Linearity (INL) is the deviation of the actual output. Both of them are calculated and reported in Fig. 32. The maximum DNL is +0. 4LSB while the maximum INL is -0. 89LSB. The process (skew) parameter files in the model directory contain the definition of the statistical distributions that represent the main process variations for the technology. This gives designers the capability of testing their designs under many different process variations to ensure that their circuits perform as desired throughout the entire range of process specifications. This is a Monte Carlo approach to the checking of designs.While being the most accurate test, it can also be time consuming to run enough simulations to obtain a valid statistical sample. Fig. 33. Monte Carlo simulation of the resolution for Vernier delay line TDC When running Monte Carlo to include FET mismatch, BOTH the Spectre mismatch and process vary statements are active. This will turn on b oth process and mismatch variations. Spectre provides the unique capability of running process variations independent of mismatch variations. This capability is not supported for this release. The average resolution calculated by averaging the delay difference between two delay lines is around 1. 66ps. The average power over one period is 148. 1E-6 W.The maximum power consumption is about 3. 6mW and the conversion time is around 2ns which is in accordance with the interfacing time estimation in system level design. Since the enable signal closed the TDC after the conversion is completed, the start signal with high frequency is prohibited to propagate so as to eliminate the unnecessary transition of delay cells and in a result saving the power dissipation. 27 4. 3 4. 3. 1 Parallel TDC Delay cells In order to design a serial of delay cells with the equal difference of delay time used in parallel TDC, the size of the transistor in a current starved structure is swept. Fig. 34. Delay ce ll in Parallel TDC 28Fig. 35. Delay time Vs width of transistor T5 Unlike Vernier TDC, only stop signal is delayed by various delay cells in parallel TDC. Thus the control of rising edge required, and then the size of transistor T5 is adjusted. As can be seen from Fig. 34, the size of transistors M1, M2, M4 and M5 is basically determined by the load capacitance which refers to the CLK pin of SAFF in this situation. Transistor T5 should be much smaller than M2 so that the discharging current could be controlled by T5. As the size of T5 increases, the delay time becomes smaller which means the delay cell is faster. According to the parameter analysis result in Fig. 5, the size of T5 can be determined by selecting the size corresponding to the delay time with 2ps difference for a serial delay cells. Fig. 36. Schematic of Parallel TDC 29 As the analysis in system level design, the delay cells are sized for delays = 0 + ? ?N. The single stop signal is delayed in parallel TDC, therefore t he matched delay cell connected to differential start signal is used to cancel the 0 and offset value. 4. 3. 2 Simulation results Similarly to Vernier TDC simulation, the input of parallel TDC, the delay difference between the start and stop signal, is swept from 0 to 20ps. The resolution and linearity are calculated and analyzed by conversion results from TDC. Fig. 37.Input of parallel TDC (stop – start) = 0ps 30 Fig. 38. Input of parallel TDC (stop – start) = 20ps The offset value of this TDC is 1 observed from Fig. 37. The result shown in Fig. 38 indicates that the start signal has passed through 11 stages of delay cells as the input is 20ps. Resolution = (20ps – 0ps)/ (11 – 1) = 2ps. 20 18 16 Output of parallel TDC (ps) 14 12 10 8 6 4 2 0 0 2 4 6 8 10 12 14 Input of parallel TDC (ps) 16 18 20 Fig. 39. Parallel TDC transfer function 31 1 INL DNL DNL and INL [LSB] 0. 5 0 -0. 5 0 2 4 6 8 10 12 Input of parallel TDC 14 16 18 20 Fig. 40. Parallel TDC linea rity DNL and INL are calculated and reported in Fig. 40. The maximum DNL is +0. LSB while the maximum INL is 1LSB. The average power over one period is 87. 33E-6 W which is much smaller than Vernier TDC. The reason is that the clock gating technology controlled by enable signal eliminates the redundant transition of delay cells. As the system level design indicates, the parallel TDC only works for 420ps each period of stop signal because that the conversion is completed instantly due to the intrinsic characteristic of parallel TDC and therefore there is no power consumption during the rest time. Although the peak power consumption is approximately equivalent to Vernier TDC, the average power dissipation is decreased dramatically. 32 Layout and post-simulation 5. 1 Layout of SAFF and post-simulation For the layout of radio frequency circuit the interconnection parasitic will be a critical problem. In an audio application for instance parasitic will probably be a minor concern. Howeve r, the operation frequency of this circuit is 5GHz which means that the interconnection parasitic will influence the performance of circuit dramatically. To minimize this influence, we could move interconnections to higher metals and make the metals carry current rather than poly. Besides, the floor plan should be as compact as possible to optimize the parasitic and impedance of interconnections. GND T0Symmetric SR Latch T15 T14 T13 T8 T9 T5 T3 Q_ T1 T12 T10 T11 T7 Q T6 T4 T2 VDD T0 T2 T4 T3 T5 T9 T1 D T6 T7 D_ CLK T8 CLK GND Sensed Amplifier Fig. 41. Floor Plan of SAFF 33 There are several steps for floor plan. First step is to examine the size of transistors and split transistor size in a number of layout oriented fingers. Then identify the transistors than can be placed on the same stack according to the principles of using almost the same number of fingers per stack and put the transistors with common drain or source together. In the floor plan shown in Fig. 41, power line VDD i s reused by SR latch and sensed amplifier to make the connections compact.Fig. 42. Layout of SAFF 34 In the development environment of Cadence 6. 1. 3, Calibre is used for DRC and Assura is used to do LVS check and RCX. Post-simulation is then performed with av_extracted view. Fig. 43. Post-simulation of sampling window Compared to Fig. 23, Fig. 43 illustrates that the timing constraint point moved from 16ps to 29ps which will affect the offset value of TDC. In addition, the delay time from clock leading edge to output Q is increased. However, this SAFF after layout can be employed to avoid meta-stability effectively due to that the sampling window is still less than 1ps. 5. 2 Layout of parallel TDC and post-simulationIn this TDC system, the clock distribution network formed as a tree distributes the signal to all the delay cells. To reduce the clock uncertainty, the network requires highly matched topology showed as Fig. 44 below. 35 Clock Fig. 44. Floor plan of Clock distribution This kind of topology guarantees the equal delay from the common point clock to each element. Fig. 45. Layout of parallel TDC After DRC and LVS, the RC net list is extracted to do post-simulation. The input of parallel TDC after layout, the delay difference between the start and stop signal, is swept from 0 to 30ps. The resolution and linearity are calculated and analyzed by conversion results from TDC. Fig. 46.Input of parallel TDC after layout (stop – start) = 0ps 36 Fig. 47. Input of parallel TDC after layout (stop – start) = 30ps The offset value of this implemented TDC is 0 observed from Fig. 46. The result shown in Fig. 47 indicates that the start signal has passed through 10 stages of delay cells as the input is 30ps. Resolution = (30ps – 0ps)/ (10 – 0) = 3ps. 35 30 Output of parallel TDC after layout (ps) 25 20 15 10 5 0 0 5 10 15 20 Input of parallel TDC after layout (ps) 25 30 Fig. 48. Parallel TDC transfer function after layout 37 0. 5 0. 4 0. 3 DNL and INL after layout [LSB] 0. 2 0. 1 0 -0. 1 -0. 2 -0. 3 -0. 4 -0. 5 INL DNL 0 5 10 15 20 Input of parallel TDC (ps) 25 30 Fig. 49.Parallel TDC linearity after layout DNL and INL are calculated and reported in Fig. 49. The maximum DNL is 0. 33LSB while the maximum INL is 0. 5LSB. The average power over one period is 442. 1E-6 W. The maxim total current is about 3. 24mA. The peak power consumption is almost the same as the TDC before layout, but there are obvious ripples even the TDC is disabled due to that the parasitic capacitors increase the time for charging and discharging. 5. 3 Comparison and analysis Technique Parallel 2-level DL parallel Pseudo-diff DL VernierGRO CMOS [ µm] 0. 065 0. 35 0. 13 0. 09 0. 09 Supply [V] 1. 2 3 1. 2 1. 3 1. 2 Power [mW] 3. 89 50 2. 5 6. 9 4. 32 Resolution [ps] 3 24 12 17 6. 4 INL/DNL 0. 5/0. 3 -1. 5/0. 55 -1. 15/1 0. 7/0. 7 – Work This [12] [3] [7] [13] Table2. Comparison to previous work Table2 compares the proposed TDC to prior pub lished work in CMOS technology. This TDC features the fastest resolution with the best linearity. The power consumption is not directly comparable because the results from the other works are corresponding to different input range. However, it still indicates that this TDC consumes very low power due to that the start signal 38 only passes two buffers and the stop signal with low frequency is delayed. The TDC error has several components: quantization, linearity and randomness due to thermal effects.As can be seen from table5, the implemented TDC achieves medium linearity which can be improved if the layout is enhanced from floor plan considering the parasitic effects. With respect to quantization noise, the total noise power generated from this kind of TDC is spread uniformly over the span from dc to the Nyquist frequency without modulation. As a result, the proposed TDC contributes the lowest noise floor due to high resolution. = =3ps, , = 20MHz, we obtain = -104. 3 dBc/Hz. Banerj ee’s figure of merit (BFM) [14], being a 1-Hz normalized phase noise floor, is defined as BFM = where is a sampling frequency of the phase comparison and N= is the frequency division ratio of a PLL.It is used to compare the phase performance of PLLs with different reference frequencies and division ratios. In this TDC based ADPLL, BFM = -225. 3dB. Even though state-of-the-art conventional PLLs implemented in a SiGe process can outperform the ADPLL presented here in the in band phase noise, -213 dB in reference and -218 dB in reference, the worst case BFM of -205 dB appears adequate even for GSM applications, since there are no other significant phase-noise contributions as in the conventional PLLs [4]. However, the Gated Ring Oscillator TDC is able to push most of the noise to high frequency region which is then filtered by the loop filter in ADPLL through holding oscillation node state between measurements.The obvious drawback of this TDC is that the dynamic range is relativ ely small which will limit the application of it. Parallel TDC is not feasible to compose the loop structure so that the area and power dissipation will be increased dramatically if larger dynamic range is required. But the Vernier TDC designed in this thesis can be used in the loop structure for large dynamic range. 39 6 Conclusion In this thesis, two kinds of Time to Digital Converters are designed with Vernier and parallel structure on schematic level respectively. The performance of these two TDCs are concluded and compared. In the Vernier TDC, only two delay cells are designed and then reused to constitute two delay lines with slightly different delay time.This architecture is easy to implement and reduces the mismatch with delay cells. But the conversion time dependent on resolution and measurement interval time is relatively long since the signals are propagating along the delay cells in serial. On the other hand, in parallel TDC, the process of conversion is completed instan taneously due to that the signals are passing through the delay cells and then captured in parallel. Thus it has lower average power dissipation over one period. However, a set of delay cells are designed which obviously introduce nonlinearities. To minimize the mismatch problem, the single stop signal is delayed instead of two input signals for avoiding the differential mismatch situation.To sum up, both of the TDCs achieve sub-gate resolution which is able to meet the application requirements and Vernier TDC has higher resolution and better linearity but longer conversion time and larger power consumption compared to parallel TDC according to the simulation results. The parallel TDC is chosen to be implemented on layout. Comparing the results from schematic simulation and post-simulation, the performance is decreased on resolution, linearity and power consumption after layout. The major reason for this phenomenon is the parasitic capacitance of transistors and real wires which is a significant factor to affect the final properties in high frequency circuits.In the stage of schematic design, the sizes of transistors are not fully considered and results in difficulties on floor plan of layout. Specifically, the transistors are rather difficult to split into the same fingers per stack and therefore the floor plan is not compact enough to minimize the interconnections. Besides, the parasitic capacitance should have been emulated on schematic simulation in order to predict the effect after layout otherwise it would be very time consuming if the schematic design is modified after layout. In addition, the size of transistors is very small which makes them comparable to wire parasitic effects. Although small transistors are with smaller parasitic capacitance and less power consumption, they will more sensitive to layout mismatch.The function of the TDCs designed and implemented in the thesis is guaranteed for the application but the performance needs to be improved. The layout turns out to be an essential stage for the final characteristics of the circuits. With a more thoughtful design flow and sophisticated consideration for mismatch, the circuits after layout could maintain the performance as schematic level. 40 7 Future work There is plenty of more work to be done to improve the performance of TDC. Due to that the TDC is essential to the aggressive goal of phase noise from all digital PLL, other kinds of architectures of it are worth to try for the required resolution and dynamic range. Since the performance of circuit after layout is not identical with schematic, the size of transistors could be modified for layout oriented. To reduce the parasitic effects, layout should be improved from a better floor plan. Vernier TDC with higher resolution and better linearity could be implemented on layout which can tolerate first order PVT variation if two delay chains are well matched [11]. Although the Vernier TDC and parallel TDC achieve high reso lution, they have very low efficiency when measuring large time intervals, which requires extra hardware and power consumption. To overcome this limitation, a Vernier Ring TDC has been proposed recently.Unlike the conventional Vernier TDC, this novel TDC places the Vernier delay cells in a ring format such that the delay chains can be reused for measuring large time intervals. Digital logic monitors the number of laps the signals propagate along the rings. Arbiters are used to record the location where the lag signal catches up with the lead signal. The reuse of Vernier delay cells in a ring configuration achieves fine resolution and large detectable range simultaneously with small area and low power consumption [11]. This architecture of Vernier Ring TDC combines the Vernier delay lines and GRO topology is worth to implement for wide application. ? ? 41 8 [1] [2] [3] [4] [5] [6] [7]